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I think what you could do is measure the bits, and then possibly flip the answer based on whether a drawn random number is less than the error rate associated with the outcome, i.e the error rates of measuring 0 but really given a 1, and measuring 1 but really given a 0. However, doing this on actual HW is a bit more tricky. Namely all of the logic needs ...


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There are two different complexity considerations that you might be interested in in this scenario. The one that most people think about is the communication complexity, i.e. how many qubits Alice and Bob have to send to the referee. This is relatively simple to calculate - it's just $mk$ where $k$ is the number of times you have to repeat the controlled-...


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The commuting model only differs from the spatial (tensor-product) model when one considers infinite-dimensional Hilbert spaces, so one would have to start with considering circuits with an infinite number of degrees of freedom. That being said, such a model has been considered in this paper and is called the $C^*$-circuit model.


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In the absence of additional assumptions, $\mathbb{E}[p_i]$ can be any real number in $[0, 1]$. For example, let $a\in[0,1]$ and define the POVM as $M_0=aI$ and $M_1=(1-a)I$. Then $$ \mathbb{E}[p_0] = \int \mathrm{tr}\left(aI|\psi\rangle\langle\psi|\right)d\psi = a \int \langle\psi|\psi\rangle d\psi = a $$ assuming the Haar measure is normalized. Similarly, ...


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tl;dr Indeed, if at any point one would need to compute and store $2^n\times2^n$ unitary of the circuit in memory that would be infeasible and render the quantum computation obsolete (it may still be useful for benchmarking NISQ computers though). Transpilation mostly works either with individual 1- and 2-qubit gates or with the whole circuit but not as a ...


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The second diagram is a classical circuit where the output of one gate is being used to drive multiple other gates. In classical digital hardware, if you increase the number if gates being driven too much, the driving gate will become too loaded and won't work as per specification. The maximum number of gates which can be driven in the Fanout of the driving ...


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"Does it mean that the second bit is also the input to the other two ancilla states?" Nothing is "input to the ancilla states". The second bit in this case, is the input to the FANOUT, whereas the first and third bits are ancillas. "Why do ancilla states require any inputs, aren't they pre-determined?" In the diagram that you ...


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A NAND gate is a universal classical gate. All boolean logic can be implemented using only NAND gates. This is clear because SOP/POS implementation needs only AND/OR/NOT and NAND can make all three of those gates as shown bellow. Quantum Computing however has the constraint/feature of requiring all operations to be reversible, and the NAND gate itself (like ...


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