When I visited the Google Hardware Lab, they were extremely secretive about everything. It is unlikely anyone will be able to answer this question except for the narrow range of Google Hardware Lab employees, and the ones I know are not very open about what Google is doing.
What I can do is answer what a different superconducting-qubit hardware company (D-Wave) does. When I did the D-Wave tour, I was shown a "wafer" which was an NxN array of 2000Q chips. So I was looking at $N\times N\times2048$ qubits. Each of these chips will have defects in random places. Some might have bad qubits only on an edge, some might have bad qubits in the middle, etc. Therefore, it is probably just good fortune that they published a paper where the bad qubit was in a convenient location. This hopefully answers your first question.
Next you ask if a bad qubit in the middle would make processing more difficult and I think the answer is yes, because middle qubits are connected to more qubits, so there's more potential gate operations which are affected.
If you want to know how many Sycamore processors are made at any given time, you'll probably need an answer from someone at the Google Hardware Lab, but D-Wave gets a new $N\times N$ array of 2000Q chips every week, where $N$ is about 10.
Are they fabricated on a wafer? D-Wave's ones are, and likely Google does the same. They are all making super-conducting qubits.
Do they pick-and-choose the Sycamore chip with the best performance? Probably the answer is "yes" because you say the bad qubit was on an edge, and the chances of that seem less likely than it being in the middle. Furthermore, it is unlikely that they had much motivation to choose a "random" chip or a "bad" chip rather than a "good" one. The company is interested in making profits, so I don't see the motivation to choose a more "fair" chip for a publication.
