# What is maximum circuit depth and size IBM Q5 and Q16 could handle?

I'm trying to implement a couple of algorithms on ibmq_16_melbourne, so I need to know if this device is able to handle with depth and size of my current circuit or not.

For example, the circuit size is 300 and depth is 99.

• Mean gate error: $$2.14 \times 10^{-3}$$ (probably higher for CX and lower for 1-qubit gates, but this information seems to be no longer available).
• Mean measure error: $$2.68\times 10^{-2}$$.

If your circuit contains $$300$$ gates then the probability that at least one gate fails is $$\begin{split} P\left(\text{at least 1 gate fails}\right) &= 1 - P\left(\text{all gates succeed}\right) \\ &= 1 - P\left( \text{1 gate succeed} \right)^{300} \\ &= 1 - \left( 1 - 2.14 \times 10^{-3} \right)^{300} \\ &\approx 0.474 \end{split}$$ This means that, without accounting for decoherence errors, your circuit fails nearly one time over two (the $$47$$% computed above does not take into account errors cancelling each other out).

Speaking now of decoherence errors, let's compute the time needed to the Melbourne chip to finish the execution of your circuit.

From the decomposition of each gate in pulse and the corresponding pulses duration (taking a rough average of $$360$$ns for CX) we have:

1. Time needed for U1: $$0$$ns (U1 is "free" in the sense that it just change the phase of the next operation).
2. Time needed for U2: $$100 + 20 = 120$$ns (one GD followed by a buffer time of $$20$$ns).
3. Time needed for U3: $$100 + 20 + 100 + 20 = 240$$ns.
4. Rough average time needed for CX: $$100 + 20 + 360 + 20 + 100 + 20 + 360 + 20 = 1000$$ns.

Depending on the number of gates in your circuit, you can compute the time needed with the function

def compute_rough_execution_time_melbourne_ns(number_of_U1: int,
number_of_U2: int,
number_of_U3: int,
number_of_CX: int) -> int:
return (0*number_of_U1 + 120*number_of_U2 + 240*number_of_U3 + 1000*number_of_CX)


Say you have a circuit of depth $$90$$ with gates from qiskit (i.e. X, Y, CX, H, ...). We will consider that the qubit on which the $$90$$ gates are applied is the "critical path", i.e. the qubit that takes the most time to reach its final state. Most of the gates in qiskit are translated to one U2 or U3, so we can say that you have approximately 90 gates that are U2, U3 or CX.

Say that you have $$80$$% of CX, $$15$$% of U3 and $$5$$% of U2. This means that you have $$72$$ CX gates, $$14$$ U3 gates and $$4$$ U2 gates. By using compute_rough_execution_time_melbourne_ns with the appropriate parameters you find that your circuit will take approximately $$75.84 \mu s$$.

Computing the decoherence errors is not easy, but knowing that the coherence times for Melbourne are $$T1 = 71.5\mu s$$ and $$T2 = 21.4\mu s$$, I would say that you have a relatively low probability to execute the whole circuit without at least one error due to decoherence.

Conclusion: without accounting for decoherence errors, you have approximately a $$50$$% chance of executing successfully the circuit. With decoherence errors, the probability is much harder to compute but I would not be surprised to see it drop to less than $$10$$%.

• You are right! I will update my answer in the next few days. In the mean time here is a quick update: it is even worse than what have been computed at the beginning (CX has an error 1 order of magnitude higher than what I used in my calculations). Mar 22, 2019 at 11:56
• @AdrienSuau, Is the probability calculation the same as you describe in your answer for the width of a circuit? For example, if I have a 4 qubit circuit with CX gates at (q0,q1) and (q2,q3) will it have the same probability of gate failure as a 2 qubit circuit with two CX gates (ignoring the fact that CX CX = I)? Jun 22, 2021 at 16:49
If your fidelity requirement is close to 100%, the maximum circuit depth that the IBM machines can handle, is zero (try just starting with $$|0\rangle$$, and then making a measurement ... you will not get back a pure zero, because the measurement fidelity in IBM machines, is an even bigger problem than gate fidelity).