I'm trying to implement a couple of algorithms on ibmq_16_melbourne, so I need to know if this device is able to handle with depth and size of my current circuit or not.

For example, the circuit size is 300 and depth is 99.


2 Answers 2


From the public data given by IBM about IBM Q16 Melbourne (14 qubits available):

  • Mean gate error: $2.14 \times 10^{-3}$ (probably higher for CX and lower for 1-qubit gates, but this information seems to be no longer available).
  • Mean measure error: $2.68\times 10^{-2}$.

If your circuit contains $300$ gates then the probability that at least one gate fails is $$ \begin{split} P\left(\text{at least 1 gate fails}\right) &= 1 - P\left(\text{all gates succeed}\right) \\ &= 1 - P\left( \text{1 gate succeed} \right)^{300} \\ &= 1 - \left( 1 - 2.14 \times 10^{-3} \right)^{300} \\ &\approx 0.474 \end{split} $$ This means that, without accounting for decoherence errors, your circuit fails nearly one time over two (the $47$% computed above does not take into account errors cancelling each other out).

Speaking now of decoherence errors, let's compute the time needed to the Melbourne chip to finish the execution of your circuit.

From the decomposition of each gate in pulse and the corresponding pulses duration (taking a rough average of $360$ns for CX) we have:

  1. Time needed for U1: $0$ns (U1 is "free" in the sense that it just change the phase of the next operation).
  2. Time needed for U2: $100 + 20 = 120$ns (one GD followed by a buffer time of $20$ns).
  3. Time needed for U3: $100 + 20 + 100 + 20 = 240$ns.
  4. Rough average time needed for CX: $100 + 20 + 360 + 20 + 100 + 20 + 360 + 20 = 1000$ns.

Depending on the number of gates in your circuit, you can compute the time needed with the function

def compute_rough_execution_time_melbourne_ns(number_of_U1: int, 
                                              number_of_U2: int,
                                              number_of_U3: int,
                                              number_of_CX: int) -> int:
    return (0*number_of_U1 + 120*number_of_U2 + 240*number_of_U3 + 1000*number_of_CX)

Say you have a circuit of depth $90$ with gates from qiskit (i.e. X, Y, CX, H, ...). We will consider that the qubit on which the $90$ gates are applied is the "critical path", i.e. the qubit that takes the most time to reach its final state. Most of the gates in qiskit are translated to one U2 or U3, so we can say that you have approximately 90 gates that are U2, U3 or CX.

Say that you have $80$% of CX, $15$% of U3 and $5$% of U2. This means that you have $72$ CX gates, $14$ U3 gates and $4$ U2 gates. By using compute_rough_execution_time_melbourne_ns with the appropriate parameters you find that your circuit will take approximately $75.84 \mu s$.

Computing the decoherence errors is not easy, but knowing that the coherence times for Melbourne are $T1 = 71.5\mu s$ and $T2 = 21.4\mu s$, I would say that you have a relatively low probability to execute the whole circuit without at least one error due to decoherence.

Conclusion: without accounting for decoherence errors, you have approximately a $50$% chance of executing successfully the circuit. With decoherence errors, the probability is much harder to compute but I would not be surprised to see it drop to less than $10$%.

  • $\begingroup$ Thank you for such developed answer! You probably speak about this information (quantumexperience.ng.bluemix.net/qx/devices) it's still available. $\endgroup$
    – C-Roux
    Commented Mar 21, 2019 at 19:28
  • $\begingroup$ You are right! I will update my answer in the next few days. In the mean time here is a quick update: it is even worse than what have been computed at the beginning (CX has an error 1 order of magnitude higher than what I used in my calculations). $\endgroup$ Commented Mar 22, 2019 at 11:56
  • $\begingroup$ @AdrienSuau, Is the probability calculation the same as you describe in your answer for the width of a circuit? For example, if I have a 4 qubit circuit with CX gates at (q0,q1) and (q2,q3) will it have the same probability of gate failure as a 2 qubit circuit with two CX gates (ignoring the fact that CX CX = I)? $\endgroup$ Commented Jun 22, 2021 at 16:49
  • 1
    $\begingroup$ No, today you have access to more precise data with Qiskit API or from IBMQ website. CNOT duration and precision changes depending on the pair of qubits it is applied on (and its orientation!) $\endgroup$ Commented Jun 22, 2021 at 18:03
  • 1
    $\begingroup$ Just do the maths with a 2 gate circuit and see what happens :) In the end, you should see that if you only consider non-correlated gate errors (not decoherence, SPAM, cross-talk, and all the other errors that might come up with real hardware) and all the qubits have the same characteristics, then it should be equivalent to apply the gates one after the other or in parallel. $\endgroup$ Commented Jun 23, 2021 at 8:17

It depends on what you mean by "able to handle". You mention a circuit depth of 99, which might be possible, but what will be the fidelity of the final state with respect to the one it's supposed to be (assuming no decoherence)?

If your fidelity requirement is close to 100%, the maximum circuit depth that the IBM machines can handle, is zero (try just starting with $|0\rangle$, and then making a measurement ... you will not get back a pure zero, because the measurement fidelity in IBM machines, is an even bigger problem than gate fidelity).

The answer to your question could be "circuit depth of 0" or "circuit depth of 99" ... it all depends on how good you want your fidelity!

  • $\begingroup$ I do not require 100% fidelity, 50% will be enough. Results that I get on Q16 are not even close to 50%. Algorithm was tested on quasm simulator and simulator returns good results. I understand that real device has limitations in connectivity and direction of CNOT operations is restricted in comparison with quasm simulator, so I've changed my algorithm due to that. It increased circuit depth from 60 to 99. I suppose that there are many other reasons that gain errors such decoherence of state as You've mentioned. Thank you for your answer! $\endgroup$
    – C-Roux
    Commented Mar 20, 2019 at 20:27
  • $\begingroup$ @ConstantineRoux. I'm glad that I could help. I will add that the biggest errors on the IBM machine are not even in the gate fidelities, but we have not even figured out a way to make measurements reliably, so right now measurement fidelities are an order of magnitude worse than gate fidelities, and you can get a poor outcome even with a circuit depth of 0. What fidelity do you get when you do no gates at all? Maybe close to 50% ? I assume after a few gates you'll quickly drop below 50%, so you might be able to answer the question yourself (about circuit depth allowing > 50% fidelity). $\endgroup$
    Commented Mar 20, 2019 at 20:39

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