# Is there something like error-suppression codes?

My question is a bit on the soft side, and basically asks if there is something between error mitigation and full error correction?

On the one hand, as far as I understand, trying to increase the quantum volume by error mitigation hits a wall based on the decoherence rates and gate errors. For instance, the recent 127-qubit simulation on IBM's chip was limited by what error mitigation can do. Adding more qubits wouldn't really help, because it was really the depth that was a key limitation.

On the other hand, having enough noisy qubits can get you to the full error correction, but the overhead is typically orders of magnitude.

Is there something in between? For example, by using codes with small distances, can we trade a dozen of physical qubits for a single composite one, which is still error-prone but less so than the original? Then we could expect a 1000-qubit chip to do things that a 100-qubit one could not. The way of packaging qubits need not even be an error-correcting code (e.g. it doesn't have to eliminate all errors up to a certain weight) but could be something like an error-suppression code, defined simply by the fact that a composite qubit is better than any individual one.

If these things have already been discussed somewhere, I'm happy to take references.

• Thanks, this is an interesting paper, with many useful references like Pivetau et al and Suzuki et al. However, they seem to stay closer to early fault-tolerant regime, where logical qubits with non-trivial distances are already available. I'm also interested if something can be done in the opposite regime, where we are only slightly beyond NISQ with 50-100 qubits, and something like a surface code with $d~11$ is not yet feasible. Jun 28, 2023 at 13:47
• Note that a $d=3$ rotated planar code consists of $18$ physical qubits. For a sufficiently good physical error rate (well below the code threshold), one could obtain logical qubits of pretty good quality. This implies that you could obtain a bunch of logical qubits for the qubit count you are discussing. Anyway, the qubit count is not the only issue here, since architectural constraints and physical error rates (hardware quality) are important for this paradigm to make sense. Jun 28, 2023 at 14:19
• Anyway, I guess that you are not interested in this. An example of a technique that is popularly considered to be an error suppression technique is dynamical decoupling (DD). Some name it as an error mitigation technique. This technique significantly increases the dephasing times of qubits. Regarding correcting all errors, note that if the HW has a considerable bias towards dephasing $T1/T2\approx 1000$, then phase flips are the dominant error source. In such case, one might obviate the bit flips by assuming that their occurrence probability is rare and correct more $Z$ errors. Jun 28, 2023 at 14:22