# Threshold estimate for 7-qubit code with flag-qubit syndrome extraction

I am looking for a paper where the threshold for 7-qubit code having a syndrome extraction based on flag qubits has been done.

In the original paper about flag qubits, there is an estimation of pseudo-threshold assuming the waiting (i.e. identity) gates are noiseless. Yet this assumption is not necessarily very good to do, especially because the number of waiting location dominates by very far the number of non-trivial gates for flag-qubit scheme. What I am looking for is a paper showing an estimate of the threshold assuming all gates (including identity) have the same error rate (which would lead to a worst-case scenario, given the sole knowledge of an error rate per gate).

Is there such a paper?

I simulated the Steane code on a nearest neighbor superconducting chip using flag qubits. The results are not published, but the thesis and all source code are available here:

https://github.com/peter-janderks/FlagBridgeQEC

To be specific, this is a subsection of the circuit I simulated: The exact circuit I used to perform fault-tolerant error correction was adaptive and depended on the measurement results of the above circuit.

The qubits are layed out as follows: The pseudo threshold I found for the steane code with all errors happening with equal probability is 0.00017. On the same layout and same error model I found a pseudothreshold of 0.00044 for the distance 3 rotated surface code.

• Thanks for the answer! In principle, the pseudo-threshold should correspond to the threshold you get for EC-Gate-EC (extended Rectangle), where EC are syndrome extraction and Gate the logical gate performed. Here, it seems you are doing something a little bit different. I would like to understand how you exactly find your threshold. Is it that you "somehow" estimate some threshold for a logical identity. Your injected state has a probability $p$ to have an error on one of its physical qubit, and you do the simulation where each gate has a probability $p$ to fail as well. Jul 1 at 15:52
• Then you compute the logical fidelity of the output state and you find the $p$ such that this logical fidelity is higher than the fidelity of doing a single physical identity on a physical qubit. Am I correct? If not could you explain a bit more the exact protocol? Thanks a lot! Jul 1 at 15:53
• I don't calculate the pseudo threshold for performing EC-Gate-EC. I compute the pseudo threshold in the same way as done in the paper you reference in your question, so by inserting errors with a probability $p$ and comparing to a bare physical qubit. Jul 6 at 16:49
• I see, thanks! So it seems that your threshold is about 10x worse than theirs (because they considered noiseless identity, but the circuits are also a bit different) Jul 6 at 18:31

In this paper, a pseudo-threshold has been computed for implementing a quantum memory "memory pseudo threshold", or a logical cNOT gate "computation pseudo threshold" for flag qubit scheme applied on the $$[[7,1,3]]$$ and $$[[9,1,3]]$$ codes for a depolarizing channel. If I am not wrong, their definition of pseudo-threshold for the cNOT is the "rigorous one", i.e. the pseudo-threshold for an exRec cNOT (i.e. a cNOT preceeded and followed by error correction).

The results are in Table III.

They also vary the amount of noise for the physical identity gates between noiseless gate, and gates as noisy as single-qubit gates ($$\gamma=0$$ means identity gates noiseless, and $$\gamma=1$$ means they are as noisy as single qubit gates).