If we do a controlled modular addition of an adder with 2n ccx and 4n cx gates for example the CDKMRippleCarryAdder
, what will be the resultant count of ccx and cx gates ? Exactly speaking what will be the count of number of ccx and cx gates when we call the circuit with CDKMRippleCarryAdder.control(1)
.
n=3
adder = CDKMRippleCarryAdder(n, kind = 'fixed')
print(adder.decompose().decompose().count_ops())
gives OrderedDict([('cx', 12), ('ccx', 6)])
controlled_adder = adder.control(1)
print(controlled_adder.decompose().count_ops())
gives OrderedDict([('ccx', 48), ('cp', 42), ('cu', 12)])
controlled_adder = adder.control(1)
print(controlled_adder.decompose().decompose().count_ops())
gives OrderedDict([('cx', 396), ('t', 192), ('p', 162), ('tdg', 144), ('h', 96), ('u', 24)])
What is the correct way to measure cx and ccx gates ? How should we actually measure the number of gates required for these circuits? And what will be or how to find the depth of adder
and controlled_adder
in terms of $n$ (what level of decompose should be applied?).