If you go to some random Majorana paper or talk, you will find a diagram like this one. Note that the diagram is using lines. Making the lines longer should exponentially increase the error suppression:
If you go to some random surface code paper or talk, you will find a diagram like this one. Note that the diagram is using square patches. Increasing the diameter of the patches should exponentially increase the error suppression:
Now, to be frank, I am really not familiar with proposals for Majorana-based qubits. And I very much expect the answer to this question to be "here is the basic fact you missed". But what I do think I understand is Majorana-based qubits are based on particles that are supposed to be analogous to the corners of surface code patches. This implies there should be strong analogies between surface code patches and the layouts of Majorana-based qubits.
What I definitely don't understand about Majorana-based qubits is why this analogy clearly breaks when it comes to the asymptotic scaling of hardware vs error suppression. Because in one context all the diagrams show linear scaling (they draw lines) and in the other context all the diagrams show quadratic scaling (they draw squares). It naively looks to me like, in order to double the code distance (square the error suppression) in these two apparently analogous systems you either:
- Double the amount of hardware (make the nanowires twice as long).
- Quadruple the amount of hardware (make the diameter of the surface code patches twice as long, allocating 4x as many physical qubits to the patch).
What are majoranas doing to improve "cost quadruples" to "cost doubles"? Why can't we also do that with surface codes?