# How to calculate the number of qubits in surface code, for given physical error rate

I am working on improvement of physical qubit error probability.

I would like to know: how to calculate the size I need for surface code, given that I need that the logical error probability will be lower than a known value "PL"?

Both reference to analytic estimated answer, and well detailed numerical solution, will be accepted. I just couldn't find one.

The current gold standard method for this is to simulate various error rates and code distances, and do a linear fit of code distance vs log logical error rate. This allows you to project the code distances needed for other error rates. For example, we did this for the surface code in "A Fault-Tolerant Honeycomb Memory" for StandardDepolarizing noise (SD6) and SuperconductingInspired noise (SI1000):

We specifically focused on projecting the number of qubits needed for the target logical error rate of 1 in a trillion:

Generally speaking this method of line fitting produces estimates along the lines of $$P_L = c \cdot (p/b)^d$$ where $$b$$ and $$c$$ are fit parameters that depend on the noise model, $$d$$ is the code distance, $$p$$ is the physical error rate, and $$P_L$$ is the logical error rate. For example, note that @3yakuya's answer starts with an estimate almost in this form.

• This is answering a case that I can assume I already have graphs with other data points - building those is the difficult part, when the fitting is the relatively easy part. I saw that you published your code, and used Stim, to build those graphs. It seems a very complicated job, since you have to write a lot of code. I am trying to learn how to use Stim, and I hope it won't take me too long. My project is not focusing on building a new topology and just wants to know the redundance in physical qubits as a function of physical error rate. Jan 13, 2022 at 11:36
• Anyway - are you recommending diving deep into Stim, and understanding how to build my own code for this purpose? Jan 13, 2022 at 11:37
• @RonCohen If you want a circuit noise threshold, you have to simulate it (in my opinion). There are too many details to track if you try to do it by hand; too many ways to miss some crucial detail that determines the dominant error mechanisms. There are other, easier, thresholds that you can compute which are more interesting theoretically than practically... but personally I've never bothered with them. Stim was designed for simulating stabilizer error correction circuits, so yes it should be helpful. Unsure if I recommend starting with these simulations, but I see them as an end goal. Jan 13, 2022 at 11:50

$$P_L \approx 0.03(p/p_{th})^{d_e}$$

$$p$$ - per-step error rate. Essentially you want to prepare some state $$|a\rangle$$ but due to imperfections you prepare $$|b\rangle$$ with probability $$p$$.

$$p_{th}$$ - threshold error rate. It's the value of $$p$$ below which logical error falls exponentially with $$d$$ and above which it increases with $$d$$.

$$d$$ - minimal number of steps (bit-flips or phase-flips) to prepare the logical operator on the logical qubit.

$$d_e$$ - $$d/2$$ for even $$d$$, $$(d + 1)/2$$ for odd $$d$$.

Therefore $$P_L$$ will scale the fastest with how many qubits you use to implement your logical qubit, but of course also depending on error rates of the hardware.

Source: Surface codes: Towards practical large-scale quantum computation (esp. eq. 11), where authors point that Analytic asymptotic performance of topological codes could be useful as well.

• Thanks. I know those formulas from the article you qouted, but there are still things that are not clear to me: 1. this formula's result does not seem to be consistent with the example given in Appendix M. 2. How to determine p_th? Jan 13, 2022 at 10:17
• Right, sorry for pehaps obvious answer then! I thought its all empirical (even the entire $P_L$) hence $p_{th}$ would be empirically determined for a given hardware errors and $d$. Jan 14, 2022 at 0:35