I get transpiled circuits using
transpile(circuit, backend=target_backend, seed_transpiler=10, optimization_level=3). I expected the resulting circuits to have the same structure for processors with the same layout. However, they do differ. For ex. circuit for Santiago has depth of 73 and includes 38 cX gates, while one for Manila has depth of 70 but with 41 cX gates. There are similar differences between other processors.
I thought it could be due to some randomness inside of the code, but the results always return the same. Does the Qiskit transpiler take into account average errors or other parameters that could affect this?