"Runtime" is not so easily quantified, it depends a lot on the compilation, the other operations in your circuit and whether you simulate or have a real backend.
Generally, the different methods trade off circuit depth (more gates, but less qubits) against circuit width (more qubits, less gates). If we define the runtime by the number of gates we need to execute, then the 'noancilla' mode would be the slowest since it has the most gates. However, if you simulate then more qubits are expensive, so using less qubits and more gates might be faster.
But there are other cases with might render the above rule of thumb invalid. The MCX could be a subroutine in a much larger circuit, so using more qubits is not a problem. Or maybe the coupling map of your device is restrictive and the Toffolis of 'v-chain' require many SWAP gates, effectively increasing the gate depth.
There are many trade offs and depending on your particular use-case either option might be the best. In the end, you can just construct the different circuits, compile them and see what gives you the smallest circuits (in depth and width).