Based on your new additional inputs, it seems like you want to transpile the individual circuit before appending them together to potentially reduce the extra work needed for the transpiler since it won't have to transpile a large circuit.
The problem that you run into then is that when you tried to transpile each individual circuit, their new transpiled circuit are mapped to different qubits, so when append them together, the qubits get mismatched, and hence changing the original circuit you had in mind.
If that is the case, then you can specify the initial layout in the transpilation process. This will make sure the qubits on each circuit will be mapped to the same target qubits.
For example:
Circuit 1:
circuit1 = QuantumCircuit(4)
for i in range(4):
circuit1.x(i)
circuit1_transpiled = transpile(circuit1, provider.get_backend('ibmq_16_melbourne') ,
initial_layout = [4,5,9,10] ,
routing_method = 'sabre')
here you still use the Sabre routing method, and the transpiled circuit is:
ancilla_0 -> 0 ─────
ancilla_1 -> 1 ─────
ancilla_2 -> 2 ─────
ancilla_3 -> 3 ─────
┌───┐
q_0 -> 4 ┤ X ├
├───┤
q_1 -> 5 ┤ X ├
└───┘
ancilla_4 -> 6 ─────
ancilla_5 -> 7 ─────
ancilla_6 -> 8 ─────
┌───┐
q_2 -> 9 ┤ X ├
├───┤
q_3 -> 10 ┤ X ├
└───┘
ancilla_7 -> 11 ─────
ancilla_8 -> 12 ─────
ancilla_9 -> 13 ─────
ancilla_10 -> 14 ─────
circuit 2:
circuit2 = QuantumCircuit(4)
for i in range(4):
circuit2.h(i)
circuit2_transpiled = transpile(circuit2, provider.get_backend('ibmq_16_melbourne') ,
initial_layout = [4,5,9,10] ,
routing_method = 'sabre')
which now also mapped to the same target qubits [4,5,9,10] as you can see:
ancilla_0 -> 0 ────────────────────────────
ancilla_1 -> 1 ────────────────────────────
ancilla_2 -> 2 ────────────────────────────
ancilla_3 -> 3 ────────────────────────────
┌─────────┐┌────┐┌─────────┐
q_0 -> 4 ┤ RZ(π/2) ├┤ √X ├┤ RZ(π/2) ├
├─────────┤├────┤├─────────┤
q_1 -> 5 ┤ RZ(π/2) ├┤ √X ├┤ RZ(π/2) ├
└─────────┘└────┘└─────────┘
ancilla_4 -> 6 ────────────────────────────
ancilla_5 -> 7 ────────────────────────────
ancilla_6 -> 8 ────────────────────────────
┌─────────┐┌────┐┌─────────┐
q_2 -> 9 ┤ RZ(π/2) ├┤ √X ├┤ RZ(π/2) ├
├─────────┤├────┤├─────────┤
q_3 -> 10 ┤ RZ(π/2) ├┤ √X ├┤ RZ(π/2) ├
└─────────┘└────┘└─────────┘
ancilla_7 -> 11 ────────────────────────────
ancilla_8 -> 12 ────────────────────────────
ancilla_9 -> 13 ────────────────────────────
ancilla_10 -> 14 ────────────────────────────
Now, we can append them together the way you did in your post:
total_transpiled_circuit = circuit1_transpiled + circuit2_transpiled
which is
q_0: ─────────────────────────────────
q_1: ─────────────────────────────────
q_2: ─────────────────────────────────
q_3: ─────────────────────────────────
┌───┐┌─────────┐┌────┐┌─────────┐
q_4: ┤ X ├┤ RZ(π/2) ├┤ √X ├┤ RZ(π/2) ├
├───┤├─────────┤├────┤├─────────┤
q_5: ┤ X ├┤ RZ(π/2) ├┤ √X ├┤ RZ(π/2) ├
└───┘└─────────┘└────┘└─────────┘
q_6: ─────────────────────────────────
q_7: ─────────────────────────────────
q_8: ─────────────────────────────────
┌───┐┌─────────┐┌────┐┌─────────┐
q_9: ┤ X ├┤ RZ(π/2) ├┤ √X ├┤ RZ(π/2) ├
├───┤├─────────┤├────┤├─────────┤
q_10: ┤ X ├┤ RZ(π/2) ├┤ √X ├┤ RZ(π/2) ├
└───┘└─────────┘└────┘└─────────┘
q_11: ─────────────────────────────────
q_12: ─────────────────────────────────
q_13: ─────────────────────────────────
q_14: ─────────────────────────────────
Thus, by specifying the initial layout you will avoid the problem of having mismatch target qubits during transpilation process.