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I am testing circuits which contain mid-circuit reset operations, using Qiskit and IBM Quantum hardware. For 2 qubit simulations, I have a reset operation on one of the qubits and would like to test having simple dynamical decoupling sequences, such as an XXYY gate sequence acting on the idle qubit. But when I transpile the circuit, this transpiles to the identity. Is there any way to keep these dynamical decoupling sequences un-transpiled without going to pulse level?

Edit: I have gotten around this by inserting barriers around the resets, breaking up the circuit according to barriers (using this How to split a Quantum Circuit on a barrier in Qiskit?), then transpiling the circuits without resets separately.

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2 Answers 2

Reset to default
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The optimization level 0 wont merge the gates:

circuit = QuantumCircuit(1)
circuit.x(0)
circuit.x(0)
transpiled = transpile(circuit, optimization_level=0)
transpiled.draw()

     ┌───┐┌───┐
q_0: ┤ X ├┤ X ├
     └───┘└───┘

Here is the documentation explaining each level:

optimization_level (Optional[int]) – How much optimization to perform on the circuits. Higher levels generate more optimized circuits, at the expense of longer transpilation time.

  • 0: no optimization
  • 1: light optimization
  • 2: heavy optimization
  • 3: even heavier optimization

If None, level 1 will be chosen as default.

If you need to preserve a particular part of the circuit but fully optimize the rest, you need to use barriers, as @Ali-Javadi suggested.

For example, let's say you want to preserve the sequence of X between the resets but optimize the rest out in the following circuit:

circuit = QuantumCircuit(1)
circuit.y(0)
circuit.y(0)
circuit.reset(0)
circuit.x(0)
circuit.x(0)
circuit.reset(0)
circuit.y(0)
circuit.y(0)

circuit.draw('mpl')

YY_reset_XX_reset_YY

You can add barriers in the following spots:

circuit = QuantumCircuit(1)
circuit.y(0)
circuit.y(0)
circuit.reset(0)
circuit.barrier(0)
circuit.x(0)
circuit.barrier(0)
circuit.x(0)
circuit.barrier(0)
circuit.reset(0)
circuit.y(0)
circuit.y(0)

circuit.draw('mpl')

same_with_barriers

Once transpiled, the resulting circuit looks like this:

transpiled = transpile(circuit, optimization_level=3)
transpiled.draw('mpl')

result

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  • $\begingroup$ Thanks, unfortunately the rest of the circuit before and after the resets need to be transpiled with a higher optimisation level. $\endgroup$
    – Hmecher
    Jun 16, 2021 at 18:37
  • $\begingroup$ I extended the answer with the barrier solution that, I think, solves your problem. $\endgroup$
    – luciano
    Jun 17, 2021 at 5:36
  • $\begingroup$ This has the DD on the same qubit after the reset though, it would need to have DD on the qubit which is not being reset. But it seems to work using reset on only part of the circuit as suggested by @Ali Javadi mentions. $\endgroup$
    – Hmecher
    Jun 18, 2021 at 1:56
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Yes put barriers between the gates which will prevent the compiler from collapsing the gates.

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  • $\begingroup$ This doesn't exactly work, since then I can have at most 2 of the gates out of XXYY being implemented concurrently with the reset. Ideally all of the dynamical decoupling will happen while the reset operation is taking place. $\endgroup$
    – Hmecher
    Jun 16, 2021 at 18:36
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    $\begingroup$ No you put the barrier just on the qubit with the DD pulses. You don't extend the barrier to other wires. circ.x(0) circ.barrier(0) circ.y(0) etc... $\endgroup$
    – Ali Javadi
    Jun 17, 2021 at 0:03
  • $\begingroup$ Ah I see. and then to align the DD pulses with the reset there would need to also be barriers around everything? $\endgroup$
    – Hmecher
    Jun 18, 2021 at 1:55
  • $\begingroup$ yes you could do that. Think of barrier as synchronizing a part of the circuit, and also preventing gates from going across it. But it's only effective on the qubits on which it is applied. $\endgroup$
    – Ali Javadi
    Jun 18, 2021 at 18:28

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